1. Field of the Invention
The present invention relates to a manufacturing method of a semiconductor device having a circuit in which a thin film transistor (hereinafter referred to as TFT) is formed on a substrate having an insulating surface. More particularly, the present invention is suitable for use in an electro-optical device typically known as a liquid crystal display device having a pixel TFT formed in a display region and a drive circuit formed in the periphery of the display region on the same substrate, and in an electronic equipment mounted with an electro-optical device with this type. Note that throughout the specification of the present invention, the semiconductor device indicates any device utilizing the semiconductor characteristics for functioning, and includes the foregoing electro-optical device and an electronic equipment mounted with the electro-optical device in its category.
2. Description of the Related Art
From the fact that a TFT having an active layer formed of a crystalline silicon film on a substrate having an insulating surface (hereinafter referred as a crystalline silicon TFT) has a high electric field effect mobility, it is possible to form a variety of functional circuits. The above electro-optical device having such functional circuits integrally formed on the same substrate has been developed. As a typical example, the active matrix liquid crystal display device is well known.
In the active matrix liquid crystal device employing the crystalline silicon TFT, a pixel TFT is formed in every pixel of an image display region and a drive circuit is formed in the periphery of the image display region. The drive circuit is composed of a shift resister circuit, a level shifter circuit, a buffer circuit, a sampling circuit, and the like in which a CMOS circuit as a basic circuit is formed. These circuits are formed on the same substrate, and formed into a unity to complete a display device.
The operating conditions of the pixel TFT and the drive circuit are not necessarily the same. From this, the characteristics that are demanded for a TFT is somewhat different. For example, the pixel TFT is demanded to function as a switch device for applying a voltage to a liquid crystal. The liquid crystal is driven by an a.c., thus a method called frame inverse drive is widely adopted. In this method, for the purpose of maintaining an electric charge of a storage capacitor, the characteristic that is demanded for the pixel TFT was to sufficiently lower an off-current value (a drain current that flows during an off-operation of TFT). On the other hand, since a high drive voltage is applied to the buffer circuit of the drive circuit, it was necessary to raise the voltage-resistance of the TFT so that it will not break when a high voltage is applied. Also, in order to make a current drive ability higher, it was necessary to sufficiently secure an on-current value (a drain current that flows during an on-operation of TFT.
However, the point at issue is that the off-current value of the crystalline silicon TFT easily rises. Moreover, similar to an MOS transistor used in an IC and the like, a deterioration phenomenon such as a drop of the on-current value is observed on the crystalline silicon TFT. This mainly results from a hot carrier implantation. It has been considered that the hot carrier generated by a high electric field in the vicinity of the drain triggers the deterioration phenomenon.
As a structure of the TFT to reduce the off-current value, an LDD region (Lightly Doped Drain) is known. In this structure, there is provided a region that is added with an impurity element at a low concentration between a channel forming region and a source region or a drain region which is formed by adding an impurity element at a high concentration, and this region is called the LDD region.
For example, Japanese Patent No. 2564725 discloses a method of manufacturing a TFT having an LDD region. In this method, a gate insulating film is formed widely in the direction of a channel width from a gate electrode, and an insulating film thinner than the gate insulating film is further formed beside this gate insulating film. Then by utilizing the difference in the thickness between this insulating film and the gate insulating film, an LDD region is formed in a semiconductor film between the end portion of the gate electrode and a source or drain region.
Moreover, as means for preventing deterioration caused by a hot carrier, a so-called GOLD (Gate-drain Overlapped LDD) structure is known in which the LDD region is arranged so as overlapping the gate electrode via the gate insulating film. With a structure of this kind, the high electric field in the vicinity of a drain is relaxed to prevent hot carrier implantation, which is effective for prevention of the deterioration phenomenon. For example, though a GOLD structure formed by a side wall which is formed of silicon is disclosed by Mutuko Hatano, Hajime Akimoto and Takeshi Sakai, in xe2x80x9cIEDM97 TECHNICAL DIGEST, p523-526, 1997,xe2x80x9d it has been confirmed that an extremely excellent reliability can be achieved when compared with TFTs of other structures.
It had been preferred that the introduction of an impurity element to the semiconductor layer, which is used to form an impurity region such as the LDD region, the source or drain region of the TFT having such a structure, be conducted in a self-aligning manner utilizing the gate electrode and the insulating film for a mask provided on the semiconductor layer. Furthermore, in order to reduce the number of masks, a method (referred as cross dope method in the present invention) has been employed in which once an impurity element of a one conductive type is introduced into the whole surface by utilizing the gate electrode and the insulating film as a mask, an impurity element of a conductive type opposite the one conductive type is introduced into the impurity region of a TFT of either the P-channel TFT or the N-channel TFT at a high concentration.
However, the characteristics being demanded for the pixel TFT and the TFT of the drive circuit such as a shift resist circuit, or a buffer circuit are not necessarily the same. For example, in the pixel TFT, a large reversal bias (negative voltage in an N-channel TFT) is applied to a gate, whereas the TFT of the drive circuit basically does not operate in the reversal bias state. Also, the operating velocity of the pixel TFT can be {fraction (1/100)} of less than that of the TFT of the drive circuit.
The GOLD structure is highly effective in preventing the deterioration of the on-current value, but on the other hand, there arises a problem in that the off-current becomes higher compared with the structure of a normal LDD. Therefore, the GOLD structure was not a preferred structure for applying to the pixel TFT. Contrarily, although the structure of a normal LDD is highly effective in suppressing the off-current value, it has a low effect in relaxing the electric field in the vicinity of a drain and in preventing deterioration caused by the hot carrier implantation. In this way, in a semiconductor device such as the active matrix liquid crystal display device that has a multiple of integrated circuits of different operating conditions, it was not always desirable to form all the TFTs with the same structure. Such a point of issue like has been revealed as an enhanced characteristic is required for the crystalline silicon TFT in particular, and as the performance demanded of the active matrix liquid crystal display device becomes increased.
Furthermore, although there are several means to decrease the off-current value of the TFT, it was necessary to form a good junction of the channel forming region and the impurity region (LDD region, source region or drain region). In order to do this, the distribution of an impurity element in the interface of the channel forming region and the impurity region that contacts the channel forming region needs to be accurately controlled. However, when the above-mentioned cross dope method is implemented, the distribution of an impurity element in the interface was difficult to control accurately since an impurity element of a one conductive type and an impurity element of a conductive type opposite the one conductive type were introduced into the impurity region of the TFT on one side.
This type of LDD structure is formed by focusing on the characteristic of the N-channel TFT. Many of the P-channel TFTs, which are formed on the same substrate to form the CMOS circuit or the like, were formed as a single drain structure for the purpose of lessening the number of masks as much as possible. In this case, there arises a problem in that since phosphorous (P) for forming an LDD in the N-channel TFT is doped into the source or drain region in the P-channel TFT, a defect is formed in the junction with the channel forming region and the off-current value increases.
A technique of the present invention is for solving the above problems, and therefore it is an object of the present invention to provide a TFT, which is to be arranged in every circuit of the semiconductor device, having an appropriate structure in accordance with a function of a circuit, to thereby improve operating characteristics and reliability of a semiconductor device.
In order to solve the above problems, according to one aspect of the present invention, there is provided a semiconductor device having a pixel TFT formed in a display region and a TFT of a drive circuit formed in the periphery of the display region on the same substrate, characterized in that: each of the pixel TFT and the TFT of drive circuit has an active layer, an LDD region formed in the active layer, a gate insulating film provided between the active layer and the substrate, and a gate electrode provided between the gate insulating film and the substrate; at least a portion of each LDD region in the pixel TFT or an N-channel TFT of the drive circuit is arranged so as to overlap with the gate electrode; and an LDD region in a P-channel TFT of the drive circuit is arranged so as to overlap with a gate electrode in the P-channel TFT. Also, it is preferable that an LDD region in each of the pixel TFT and the N-channel TFT of the drive circuit is arranged so as not to overlap with a channel protection insulating film, and to overlap with a gate electrode by at least a portion thereof; and an LDD region in a P-channel TFT of the drive circuit is arranged so as to overlap with a channel protection insulating film in the P-channel TFT of the drive circuit, and to overlap with a gate electrode in the P-channel TFT.
Further, according to another aspect of the present invention, a P-channel TFT of the drive circuit has a first impurity region containing therein both an impurity element that gives p-type and an impurity element that gives n-type and a second impurity region containing therein an impurity element that gives p-type, and is characterized in that the second impurity region is formed between the first impurity region and an LDD region in the P-channel TFT of the drive circuit.
This is so constructed that phosphorous that is doped into a source or drain region of a P-channel TFT is not doped into the junction with the channel forming region without increasing the number of masks, attaining a reduction of an off-current value.
A storage capacitor connected to the pixel TFT includes a capacitor wiring formed over the substrate, an insulating film formed on the capacitor wiring, and a semiconductor layer formed on the insulating film. Alternatively, an organic resin film is formed on the pixel TFT, and a capacitor includes a light shielding film formed on the organic resin film, a dielectric film formed closely to the light shielding film, and a pixel electrode connected to the pixel TFT, a portion of which overlaps with the light shielding film.
Moreover, in order to solve the above problems, the present invention provides a method of manufacturing a semiconductor device having a pixel TFT formed in a display region and a TFT of a drive circuit formed in the periphery of the display region on the same substrate, the method comprising the steps of: forming an LDD region in the pixel TFT or an N-channel TFT of the drive circuit at least a portion of which overlaps with a gate electrode; and forming an LDD region in a P-channel TFT of the drive circuit that overlaps a gate electrode in the P-channel TFT. Further, the method may comprises the steps of: forming an LDD region in the pixel TFT and an N-channel TFT of the drive circuit so as not to overlap with a channel protection insulating film, and to overlap with a gate electrode by at least a portion thereof; and forming an LDD region in a P-channel TFT of the drive circuit in a manner so as to overlap with a channel protection insulating film in the P-channel TFT, and to overlap with the gate electrode in the P-channel TFT.
The above method of manufacturing a semiconductor device further comprises the step of: forming a first impurity region containing therein both an impurity element that gives p-type and an impurity element that gives n-type therein and a second impurity region containing therein an impurity element that gives p-type therein in the P-channel TFT of the drive circuit, and the second impurity region is preferably formed between the first impurity region and an LDD region in the P-channel TFT of the drive circuit.
Further, according to another aspect of the present invention, a method of manufacturing a semiconductor device having a pixel TFT formed in a display region and a TFT of a drive circuit formed in the periphery of the display region on the same substrate is characterized in that the method comprises: a first step of forming gate electrodes on a substrate; a second step of forming a gate insulating film on the gate electrodes; a third step of semiconductor layers on the gate insulating film; a fourth step of forming channel protection films on the semiconductor layers; a fifth step of introducing an impurity element that gives n-type into the semiconductor layers, and forming LDD regions in an N-channel TFT that does not overlap with the channel protection films; a sixth step of introducing an impurity element that gives n-type into the semiconductor layers, and forming a source region or a drain region on the N-channel TFT; and a seventh step of introducing an impurity element that gives p-type into one of the semiconductor layers, and forming an LDD region, and a source region or a drain region in the P-channel TFT that overlaps with the channel protection film.
The above method of manufacturing a semiconductor device is characterized by further comprising the steps of: forming a capacitor wiring on the substrate; forming an insulating layer on the capacitor wiring; forming a semiconductor layer on the insulating layer; and forming a storage capacitor connected to the pixel TFT. The method further comprises the steps of: forming an organic resin film on the pixel TFT; forming a light shielding film on the organic resin film; forming a dielectric film on the light shielding film; and forming a pixel electrode connected to the pixel TFT, a portion of which overlaps with the light shielding film; forming a capacitor therefrom. The light shielding film is formed of one or plural kinds of materials selected from aluminum, tantalum, and titanium, and the dielectric film is preferably formed of an oxide of a material which the light shielding film is formed of. Most preferably, this oxide is formed by anodic oxidation.